Design of radar pulse compression system based on

  • Detail

Design of radar pulse compression system based on FPGA

pulse compression technology refers to the realization process of modulating the wide pulse signal transmitted by the radar (such as linear frequency modulation, nonlinear frequency modulation, phase coding), and obtaining the narrow pulse after pulse compression processing the echo wide pulse signal at the receiving end. Pulse compression effectively solves the contradiction between the radar range and range resolution of the general wheel and spoke sensor, and can improve the range resolution under a certain range

pulse compression of LFM signal

the process of pulse compression is realized by convoluting the received signal s (T) with the pulse response H (T) of the matched filter. When processing digital signals, the pulse compression process is realized by convoluting the echo sequence s (n) with the impulse response sequence H (n) of the matched filter. The output of the matched filter is:


the implementation method according to formula (1) is called time domain correlation method. According to Fourier transform theory, time-domain convolution is equivalent to frequency-domain multiplication. Therefore, equation (1) can be realized in frequency domain by fast Fourier transform (FFT) and inverse transform (IFFT), which is called frequency-domain fast convolution method

the basic principle of realizing digital pulse compression with frequency domain method is to first perform fast Fourier transform (FFT) on the external sampled signal to obtain the echo signal spectrum s (W), then multiply s (W) with the matched filter spectrum H (W), and finally perform inverse fast Fourier transform (IFFT) on the product result to obtain the pulse compression result y (n), which is expressed as


the principle of frequency domain fast convolution method is shown in Figure 1, The matched filter transfer function H (k) is stored in the memory

Figure 1. The curve of frequency domain pulse compression principle block diagram automatically follows

according to the matched filtering theory, the pulse response H (n) of the digital matched filter requires that for the foam granulator and the transfer function H (k) is

H (n) = S1 (-n), H (k) = S1 (k) (3)

, where s (n) is the radar transmission signal sequence; S (k) is the spectrum of signal sequence

digital pulse compression system

1 system composition and hardware design

this system is a part of the monopulse radar signal processor. Because the range, azimuth/pitch signals that monopulse radar needs to process come from the target reflection echo of the same transmitting signal source, it is required to carry out simultaneous, same frequency ADC sampling and pulse compression processing with the same algorithm on the two signals. In view of this characteristic, the radar digital pulse compression system moves the same pulse compression processing function into two FPGA chips. Due to the special requirements of radar volume, weight, power consumption and other indicators, the system adopts the hardware structure of two channels of pulse compression processing, that is, the azimuth and pitch signals share a pulse compression channel in time sharing. The hardware structure of radar signal processing subsystem is shown in Figure 2

Figure 2 hardware structure diagram of radar signal processing unit

in the system, the data is divided into sum and difference (including heading difference and pitch difference) after sampling, which are input into two FPGAs respectively for pulse compression calculation, and then sent to the back-end DSP for spectral analysis to determine the distance, speed, orientation and other conditions of the target. From the block diagram, we can see that FPGA not only does pulse compression calculation for data, but also undertakes the tasks of input data processing and reading and writing status registers. The status register stores the control parameters of pulse compression calculation, and the back-end DSP controls it according to the analysis results

2 software design

according to the characteristics of the bit operation structure and the advantage of rich block ram resources embedded in the chip, the pulse compression system adopts the ping-pong operation of two memories to make two ports of a dual port RAM in the read or write state at the same time in each level of FFT operation, so as to meet the need of outputting two operands per clock cycle. Moreover, the data is written into another dual port RAM with the same address after the butterfly computing unit operation, which saves the time of writing address generation, and provides the possibility of designing a high-speed FFT system

as shown in Figure 3, two pieces of intermediate ram, Rama and RAMB, are used to complete the ping-pong operation. The read address generated by the address generation module is simultaneously connected with the two pieces of RAM in the intermediate stage to control the operands required for the corresponding ram reading. The operands are written to the two ports of the other piece of RAM in the same address mode after being calculated by the butterfly computing module. The reading and writing of ram is controlled by the write enable signal generated by the address generation module. The ram write enable in the read state is set to zero, while the write enable end of the other piece is set to high and is in the write state. Moreover, the output port does not output when the ram is set to the write state, so as to reduce the number of ram reads. In this way, the input ram becomes the output RAM, and the output RAM becomes the input ram. Repeat until the last stage of FFT

Figure 3 structural block diagram of pulse compression system

pressure needs to be supplemented immediately. After each level of FFT operation, the functions of the two ram are interchanged, the write enable is reversed, and the operation is completed. Each output data of ram needs to pass through the data selection module (datamux), which is controlled by the current stage signal output by the address generation module. The system adopts three FFT modes: 1024 points, 512 points and 256 points, all of which use the same rotation factor ROM. According to the different FFT points, the read address of ROM, expandr, is adjusted accordingly. This design also saves block ram resources in the chip to a great extent

3 system performance

in view of the requirements of the radar signal processor for real-time and high precision, we have designed and developed a high-performance pulse with independent intellectual property rights

Copyright © 2011 JIN SHI